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ahb_ram
- AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such
VGA
- 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
Dual_port_RAM
- 很精彩的双端口RAM应用笔记，对搞单片机、FPGA的都有帮助。-dual_port_ram
program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
BlockRAM
- xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
DoubleDort_RAM
- 双口RAM控制时序仿真 双口RAM控制时序仿真 -Control of dual-port RAM dual-port RAM timing simulation control timing simulation to control dual-port RAM Timing Simulation
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
ram_old
- 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
rom
- 根据实验要求，对rom和ram进行验证，实现各项功能。-According to the experimental requirements of rom and ram for authentication, the realization of various functions.
wave_produce_VHDL
- --文件名：mine4.vhd。 --功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节
FIFO
- FIFO中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
profiles
- source code of counter,ram,lfsr etc
USB2RAM
- Module usb ram - bardzo uzyteczny do komunikacji z innymi urzadzeniami-Module usb ram- bardzo uzyteczny do komunikacji z innymi urzadzeniami
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
sj_work
- RAM控制的VHDL实现 真的很有用 -VHDL implementation of the RAM control true true useful useful
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi